In the development of an electronic circuit using a conventional computer-aided design (CAD), an arrangement design is performed in a procedure illustrated in, for example, FIG. 1 after a circuit design.
(1) A designer mainly obtains connection information between terminals of components from a logic diagram 101.
(2) The designer classifies manually the components into several groups on the basis of the connection information between the terminals.
(3) The designer manually arranges the components on a substrate 102 on a group-by-group basis.
(4) The designer moves the components arranged on the substrate 102 again or cancels the arrangement of the components by taking into account various conditions such as wiring property or heat generation.
Since a component arrangement method differs from each designer, the arrangement design may be performed in a different procedure.
A development flow of a printed circuit board having many variations is known. In the development flow, the printed circuit board is developed in the sequence of a circuit design, a printed circuit board design, a printed circuit board manufacturing, a component mounting, and an operation confirmation.
A component arrangement scheme of a printed wiring board designing system is also known. In the component arrangement scheme, connection information of unarranged components are read in a descending order of degrees of connection relationship regarding a designated arranged component, and an outer appearance of an unarranged component and connection relationship between the unarranged component and the designated arranged component are displayed on a display area.
There is also known, for determining an arrangement of pins of a large scale integrated circuit (LSI) for example, an interactive LSI pin floor planner. The LSI pin floor planner displays arrangement states of temporarily determined pins of an LSI to be designed on a first window of a display screen. Further, the LSI pin floor planner displays, on a second window, arrangement states of the LSI to be designed and another LSI or the like on a package and a ratsnet indicating a connection relationship between pins of the LSI to be designed and pins of the other LSI or the like. When an instruction to change the arrangement of the pins of the LSI to be designed, the arrangement states of the pins are changed in the first window as instructed and the ratsnet within the second window is also changed simultaneously.
Related techniques are disclosed in, for example, Japanese Laid-Open Patent Publication No. 02-217967 and Japanese Laid-Open Patent Publication No. 06-301745.
A related technique is also disclosed in a non-patent literature, i.e., “a development flow of a printed circuit board having many variations”, Komatsu Shinichi, Design Wave Magazine No. 21 (CQ Publishing Co., Ltd), pp. 49-50, May. 1999.
In an arrangement design using the conventional CAD, in a case where there are many kinds of large number of components which are packed into a substrate at a high density, there is a tendency that a work amount by a designer needed for a component arrangement is increased and working hours are lengthened due to the difficulty of packing the components into the substrate at a high density.
Such a problem is not limited to a case where components are intended to be arranged on a printed circuit board and also occurs in a case where components are intended to be arranged on a semiconductor substrate such as an LSI.